This invention relates to cross-connect systems and, more particularly, to large time/space switch fabrics.
Digital cross-connect systems are commonly employed to controllably rearrange and redirect the contents of signals being communicated in digital transmission systems. However, with ever increasing demands for larger transmission capacity, there is a need for increasingly larger capacity non-blocking switch units used in the cross-connect switching fabric.
There are several known approaches that may be employed to realize cross-connect switching fabrics. One such approach employs an array of n:1 multiplexors, where xe2x80x9cnxe2x80x9d is the capacity of the cross-connect switching fabric. Unfortunately, the size of such multiplexor arrays grows exponentially with xe2x80x9cnxe2x80x9d and each of the inputs of the array suffers a load that grows linearly with xe2x80x9cnxe2x80x9d.
In another prior known approach, inputs are time multiplexed and, then, stored in an array of storage elements, typically a random access memory (RAM) unit. The RAM unit size is twice the number of signal elements to be switched, i.e., cross-connected, so that an entire complement of input signal elements can be read by out ports in an arbitrary order, while a new complement is being simultaneously being stored. As the capacity of the switching fabric increases, the number of different signal elements arriving per unit of time increases, and the size of the RAM unit and the speed of its write and read ports must also increase.
Moreover, in such arrangements, the size of the signal elements affects the size of the RAM unit and the access cycle time. In order to minimize the through put delay of the switching fabric, it is necessary to reduce the size of the signal elements which, in turn, increases the frequency at which elements from each signal must be accessed to maintain the cross-connected signals. Indeed, it is desirable to access an entire signal during a write or read cycle. Clearly, in this arrangement, the cross connect write/read port capacity becomes a bottleneck thereby limiting the size of such RAM based cross-connect systems.
Indeed, the size of available RAM units and their access time limit the capacity of known cross-connect switching fabrics. As indicated above, as the size of the RAM units increases, the access time of the RAM units also increases. Consequently, there is a fundamental limitation of the capacity of prior known cross-connect switching fabrics employing RAM units. Additionally, the access time of the RAM units is dominated primarily by the need for write address decoding, read address decoding or both to provide unrestricted access to the stored contents of the entire RAM. As the size of the RAM increases, the number of address decoding stages, select lines and inputs for each of a plurality of so-called sense amplifiers increases which, in turn, slows down each phase of the data access operation of the cross-connect switching fabric.
These and other problems and limitations of prior known digital cross-connect switching fabrics are overcome by employing at least one multi-port RAM switch unit to realize a non-blocking cross-connect space-time switching fabric. The at least one multi-port RAM switch unit has a plurality of write circuits and a plurality of read circuits, each of which operates at a timing rate that is a prescribed fraction of the input/output clock rate of the input/output ports of the multi-port RAM based cross-connect switching fabric. Additionally, in one embodiment, each of the write circuits only needs partial access to non-overlapping storage positions and each of the read circuits has independent and unrestricted access to all data storage positions in each of a plurality of storage units that make up the at least one multi-port RAM switch unit. Because the write circuits and each of the read circuits are operating at the prescribed fraction of the multi-port RAM switch unit input/output clock rate, a multi-port RAM based cross-connect switching fabric is realizable which has a significantly larger storage capacity that is accessible within a reasonable access time.
In one embodiment of the invention, a plurality of multi-port RAM switch units is employed to realize a multi-port RAM based non-blocking cross-connect switching fabric.
In a specific embodiment, the fractional write rate is exploited so that a single write circuit can serve a plurality of input ports. In this manner incoming signal elements that were arrayed in space are converted to signal elements arrayed in time. Moreover, the space diversity of the incoming signal elements is further exploited by employing a plurality of write circuits each of which has access to a common write address space. Specifically, each write circuit is assigned exclusive access to a particular segment of the write address space that is different from that assigned to any other write circuit. The signal elements that are supplied through a particular write circuit are written into the segment of memory locations of the multi-port RAM switch unit assigned to that particular write circuit. When the write address space is completely full, the entire capacity of the input ports is collected in a single memory address space in a predetermined order. Then, this write address space becomes the read address space, while the former read address space now becomes the write address space to be employed while writing newly arriving input signal elements.
Furthermore, since the read circuits are operating at a fraction of the output port clock rate, each of the read circuits can serve a plurality of output ports by delivering read signal elements from the multi-port RAM switch unit to the output ports in a round robin fashion. Additionally, in another embodiment of the invention, each read circuit is assigned exclusive access to a particular segment of the read address space that is different from that assigned to any other read circuit.
Consequently, the capacity of the multi-port RAM based cross-connect switching fabric is markedly increased. Employing separate write input ports and read output ports doubles the cross-connect capacity of the multi-port RAM switch unit. The addition of a second write input port and read output port pair further doubles the cross-connect capacity of the multi-port RAM switch unit. Adding further write input port and read output port pairs proportionately increases the cross-connect capacity of the multi-port RAM switch unit in a linear fashion.